This blog will look at recent developments in RISC-V and in particular at announcements by Western Digital at the 2018 RISC-V Summit in Santa Clara, CA. At the RISC-V summit, Western Digital announced three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. Western Digital say that is it planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. According to Western Digital, the company utilized the SweRV ISS to rigorously simulate and validate the SweRV Core, with more than 10 billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help accelerate the industry’s move to an open source instruction set architecture.

Source: Forbes December 11, 2018 04:07 UTC